1. Field of the Invention
The present invention relates to a processing apparatus which can perform a product summation operation at a high speed for, for example, linear interpolation, correction, etc. The present invention also relates to an image processing apparatus suitable for generating three-dimensional images in the field of computer graphics etc.
2. Description of the Related Art
Computer graphics are often used in a variety of computer aided design (CAD) systems and amusement machines. In particular, systems using three-dimensional computer graphics have spread rapidly, along with the recent advances in image processing technology.
In three-dimensional computer graphics, one of the most widespread techniques used is the polygon rendering system. In such a system, a three-dimensional model is expressed as an composite of triangular unit graphics (polygons). The polygons are drawn, the colors of the pixels of the display screen are decided, and then the model is displayed on the display screen.
In such rendering processing, for example, when generating pixel data between the vertexes of the triangles or inside the triangles based on the vertexes, processing for linear interpolation is performed frequently at the time of giving highlighting to the texture data, at the time of texture mapping, and at the time of giving a fog effect.
The processing for linear interpolation performed in such a case can be expressed by the following formula 1:
Axc3x97xcex1+Bxc3x97(1xe2x88x92xcex1)xe2x80x83xe2x80x83(1)
When performing the signal processing for linear interpolation as shown in formula 1, a configuration using two multipliers and one adder or a configuration using one multiplier, one subtractor, and one adder can be easily considered in an ordinary case.
Also, a configuration can be considered using the processor shown in FIG. 5.
In the processor shown in FIG. 5, the operation [Axc3x97xcex1+Bxc3x97(1xe2x88x92xcex1)] can be developed to the operation [Axc3x97xcex1+Bxc3x97xe2x88x92xcex1+B] (where xe2x88x92xcex1 indicates a bit inversion of xcex1) and evaluated by adding the adding term B and partial products outxe2x80x940 to outxe2x80x947 selected corresponding to the bits of the variable a to the values shifted as shown in FIG. 5.
Note that the partial products outxe2x80x940 to outxe2x80x947 are values obtained for each bit of xcex1 by selecting A when the bit is xe2x80x9c1xe2x80x9d and selecting B when the bit is xe2x80x9c0xe2x80x9d.
When performing the ordinary processing for linear interpolation as shown in formula 1 in an 8-bit processing system wherein, for example, the variables are 8-bit variables, if A=1, xcex1=1, and B=0 and performing normal multiplication, the operation shown in formula 2 is performed. When outputting the upper 8 bits as the result of the multiplication, the result is 0xc3x97FE.
0xc3x97FFxc3x970xc3x97FF+0xc3x97(1xe2x88x920xc3x97FF)=0xc3x97FE01xe2x80x83xe2x80x83(2)
Note that FF indicates a hexadecimal number.
When mathematically considering 0 to 1.0 corresponding to 0xc3x9700 to 0xc3x97FF, 1.0xc3x971xe2x89xa01.0 is obtained, which means that the correct result of the operation can no longer be obtained.
Accordingly, for example, when applying this processing for linear interpolation to the fogging of the above three-dimensional computer graphics system, even when setting the fog coefficient to 1.0 so as not to give any fog effect at all, there is the problem that the input original pixel data is affected by something or another and the original pixel data cannot be maintained.
Therefore, up until now, use has been made of the result of the operation output from the processor shown in FIG. 5 corrected when xcex1=1.0. With this, however, there is the problem that the size of the circuit becomes large. Especially, recently, there is a demand for forming such a processing circuit on an integrated circuit. In this case, there is the problem that the provision of the correction circuit outside the integrated circuit enlarges the size of the device, while provision inside enlarges the area of the circuit on the chip. It is desired to eliminate these problems in the circuit configuration.
When forming such an image processing circuit for a three-dimensional computer graphic system on an integrated circuit, it is desired to perform the product summation operation using such a linear interpolation processor. Until now, however, two stages have been usedxe2x80x94a part for calculating the product and a part for calculating the sumxe2x80x94and therefore two processors are required. Therefore, it has been desired to make improvements in the circuit size and processing speed.
An object of the present invention is to processing apparatus for linear interpolation perform operations for obtaining original data suitable even when the interpolation coefficient xcex1=1.0, which can perform a product summation operation at a high speed, and which is suited for formation on an integrated circuit without increasing the size of the circuit much at all.
Another object of the present invention is to provide an image processing apparatus which uses such a processing apparatus and consequently can perform, for example, texture mapping, fogging, highlighting, and other image processing efficiently at a high which is suited for to formation on an integrated circuit.
The present inventors considered the fact that the error explained above was caused since it was attempted to make 0xc3x97FF (255) correspond to 1.0 in the value a and theorized that it would be possible to eliminate the error by further adding A so that [xcex1+1] became 256. Then, they discovered that addition of A was possible by switching the +B term to +A in the basic formula of the circuit shown in FIG. 5, that is, [Axc3x97xcex1+Bxc3x97xe2x88x92xcex1+B], in the case of xcex1=1.0. They further added a new term for carrying out a product summation operation and invented a processing apparatus capable of performing correction multiplication, processing for linear interpolation, and a product summation operation and an image processing apparatus capable of suitably using the processing apparatus for image processing.
Accordingly to a first aspect of the present invention, there is provided a signal processing apparatus for performing the operation [Axc3x97xcex1+Bxc3x97(1xe2x88x92xcex1)], wherein A and B are any values of a predetermined bit and xcex1 is a coefficient with a value of 0xe2x89xa6xcex1xe2x89xa61 of a predetermined bit width. The signal processing apparatus then obtains; the upper bits of the result of the operation. The signal processing apparatus includes (1); an added value selecting means for selecting the value A as the added value F when xcex1=1 and selecting the value B as the added value F when xcex1xe2x89xa01; (2) and a processing means for performing the operation [Axc3x97xcex1+Bxc3x97xe2x88x92xcex1+F] (where xe2x88x92xcex1 indicates a bit inversion of xcex1) based on the selected added value F.
Preferably, the processing means comprises (1) a partial product generating means for selecting the value A when the bit is 1 and selecting the value B when the bit is 0 for each bit of the coefficient a and generating a partial product by shifting the selected value to a position corresponding to the bit of the xcex1; and (2) an adding means for adding the selected added value F and the generated partial products of the number of bits of the xcex1.
Preferably, the adding means is configured by a Wallace-tree type architecture comprised of one-bit adders in a tree structure.
According to a second aspect of the invention, there is provided a signal processing apparatus for performing the operation [Axc3x97xcex1+Bxc3x97(1xe2x88x92xcex1)+C], where A, B, and C are any values of a predetermined bit width and xcex1 is a coefficient with a value 0xe2x89xa6xcex1xe2x89xa61 of a predetermined bit width, and for obtaining the upper bits of the result of the operation. The signal processing apparatus includes (1); an added value selecting means for selecting the value A as an added value F when xcex1=1 and selecting the value B as the added value F when xcex1xe2x89xa01; and (2) a processing means for performing the operation [Axc3x97xcex1+Bxc3x97xe2x88x92xcex1+F+C] (where xe2x88x92xcex1 indicates a bit inversion of xcex1) based on the selected added value F.
Preferably, the processing means comprises (1) a partial product generating means for selecting the value A when the bit is 1 and selecting the value B when the bit is 0 for each bit of the coefficient xcex1 and generating a partial product by shifting the selected value to the position corresponding to the bit of the xcex1; and (2) an adding means for adding the selected added value F. the generated partial products of the number of bits of the xcex1, and the value C.
Preferably, the added value selecting means, the processing means, the partial product generating means, and the adding means are formed as an integrated circuit.
According to a third aspect of the invention, there is provided an image processing apparatus, comprising a processing apparatus for performing the operation [Axc3x97xcex1+Bxc3x97(1xe2x88x92xcex1)], wherein A and B are any values of a predetermined bit width and xcex1 is a coefficient of a value of 0xe2x89xa6xcex1xe2x89xa61 of a predetermined bit width, and for obtaining the upper bits of the result of the operation. The processing apparatus includes (1); an added value selecting means for selecting the value A as the added value F when xcex1=1 and selecting the value B as the added value F when xcex1xe2x89xa01; and (2) a processing means for performing the operation [Axc3x97xcex1+Bxc3x97xe2x88x92xcex1+F] (where xe2x88x92xcex1 indicates a bit inversion of xcex1) based on the selected added value F and (3) an input control means for respectively inputting to the processing apparatus texture mapping data as the value A, the image data of the side on which the texture is applied as the coefficient xcex1, and 0 as the value B during a predetermined first mode.
Preferably, the input control means inputs to the processing apparatus pixel data as the value A, a fog coefficient as the coefficient xcex1, and a fog color as the value B during a predetermined second mode.
Preferably, the processing means comprises (1) a partial product generating means for selecting the value A when the bit is 1 while selecting the value B when the bit is 0 for each bit of the coefficient xcex1 and generating a partial product by shifting the selected value to the position corresponding to the bit of the xcex1; and (2) an adding means for adding the selected added value F and the generated partial products of the number of bits of the xcex1.
According to a fourth aspect of the invention, there is provided an image processing apparatus, comprising a processing apparatus for performing the operation [Axc3x97xcex1+Bxc3x97(1xe2x88x92xcex1)+C], wherein A, B, and C are any values of a predetermined bit width and xcex1 is a coefficient of a value of 0xe2x89xa6xcex1xe2x89xa61 of a predetermined bit width and for obtaining the upper bits of the result of the operation. The processing apparatus includes (1); an added value selecting means for selecting the value A as an added value F when xcex1=1 and selecting the value B as the added value F when xcex1xe2x89xa01; and (2) a processing means for performing the operation [Axc3x97xcex1+Bxc3x97xe2x88x92xcex1+F+C] (where xe2x88x92xcex1 indicates a bit inversion of xcex1) based on the selected added value F; and (3) an input control means for inputting to the processing apparatus texture mapping data as the value A, image data of the side on which the texture is applied as the coefficient xcex1, and 0 as the values B and C during a predetermined first mode.
Preferably, the input control means inputs to the processing apparatus pixel data as the value A, a fog coefficient as the coefficient xcex1, a fog color as the value B, and 0 as the value C during the second mode.
Preferably, the input control means inputs to the processing apparatus texture mapping data as the value A, a value indicating an ambient light as the coefficient xcex1, 0 as the value B, and a value indicating a specific light source as the value C during a predetermined third mode.
Preferably, the processing means comprises (1) a partial product generating means for selecting the value A when the bit is 1 and the value B when the bit is 0 for each bit of the coefficient xcex1and for generating a partial product by shifting the selected value to the position corresponding to the bit of the xcex1 and (2) an adding means for adding the selected added value F, the generated partial product of the number of bits of the xcex1, and the value C.
Preferably, the means are formed on an integrated circuit.